Project name is a user selected name and the location is the directory where the source files are
The create project window consists of several fields: project name, project location, default library name, and copy To create a project in ModelSim, select New > Project. Of the simulation, the design can be altered until it meets the desired specifications. We compile the design and then run the simulation. We begin by creating a project whereĪll design files to be simulated are included. To perform simulation with ModelSim follow a basic flow shown in Figure 1. Finally, the command prompt at the bottom shows feedbackįrom the simulation tool and allows users to enter commands. The work area on the right is the space where windowsĬontaining waveforms and/or text files will be displayed. To you, as well as details of the project you are working on. The workspace contains a list of modules and libraries of modules available The menu is used toĪccess functions available in ModelSim. Workspace tabs on the left, a work area on the right, and a command prompt at the bottom. The ModelSim program window, shown in Figure 7, consists of four sections: the main menu at the top, a set of
We begin this tutorial by showing how to perform a functional simulation of the example design. We begin by describing a procedure to perform a functional simulation, and then discuss how to perform a
In the following sections, we use the serial adder example to demonstrate how to perform simulation using ModelSim. Quartus II project for this design has been created as well. The design is located in the example/functional and example/timing subdirectories provided with this tutorial. Registers, an adder and a finite state machine (FSM) to control this design.įigure 6. It consists of the instances of the shift
The Verilog code for the top-level module of this design is shown in Figure 3. Of A and B have been added, the circuit stops and displays the sum until a new addition is requested.įigure 2. Time the least-significant bits of A and B are added and the result is stored into the shift register sum. After the st ar t signal is set high, these registers are shifted right one bit at a time. The shift registers A and B are loaded with the
It consists of three shift registers, a full adder, a flip-flop to storeĬarry-out signal from the full adder and a finite state machine (FSM). The result of the operation is stored in a 9-bit sum register.Ī block diagram of the circuit is shown in Figure 2. It takes 8-bit inputs A and B and adds them in a serial fashion when the g o
Software, or ModelSim-Altera software that comes with Quartus II, to work through the tutorial.
You need Quartus II CAD software and ModelSim In this tutorial, we show how to simulate circuits using ModelSim. Simulation however, it takes longer to perform. This type of simulation is more realistic than the functional The circuit, it shows the timing of signals in the circuit. In addition to testing the logical operation of Logic components and wires take some time to respond to input stimuli. It is a more complex type of simulation, where The second step of the simulation process is the timing simulation. This simulation is fast and useful for checking the fundamental correctness of the Signals are propagated through the circuit using Operation of a circuit without accounting for delays in the circuit. The functional simulation tests the logical There are two main types of simulation: functional and timing simulation. The general flow of a simulation is shown in Figure 1. The output of a simulation is a set of waveforms that show how aĬircuit behaves based on a given sequence of inputs. Inputs to a circuit and observing its behavior. To verify that a design operates correctly we use simulation, which is a process of testing the design by applying Of many modules, each of which has to be tested in isolation and then integrated into a design when it operates U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS FOR A LTERA FPGA D EVICESĭesigners of digital systems are inevitably faced with the task of testing their designs. The reader is expected to have the basic knowledge of Verilog hardware description language, and the Altera Quartus How to perform functional and timing simulations of logic circuits implemented by using Quartus II CAD software. This tutorial is a basic introduction to ModelSim, a Mentor Graphics’ simulation tool for logic circuits.